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preliminary data sheet al2100 al2100-ds01-r 16215 alton parkway ? p.o. box 57013 irvine, ca 92619-7013 phone: 949-450-8700 fax: 949-450-8710 11/11/02 ultra low-power 100 mbps ethernet media converter figure 1: system block diagram general description features the al2100 is designed for media converter applications. it is intended for 100 mbps fast ethernet fiber optic-to- twisted pair media converter designs. the device provides a pecl interface for use with media connectors such as the 1300 nm fiber optic module. the al2100 is compatible with ieee 802.3 100base-fx and 100base-tx standards. the al2100 provides additional functionality such as fault propagation, redundancy for fault-tolerant system design, and remote loopback for diagnostic support. ? power supply: 2.5v 100 mbps media converter: fiber-to-fiber or fiber-to- twisted pair full duplex or half duplex auto-negotiation on twisted pair phy 48-pin tqfp industrial temp (-40 c to +85 c) 0.25 m cmos fully compliant with ieee 802.3 / 802.3u baseline wander compensation multifunction led outputs hp auto-mdi/mdix diagnostic register fault propagation redundancy for fault tolerant system design 100base-tx transceceiver clock recovery descrambler elastic store scrambler elastic store clock recovery txp txn rxp rxn fx transceiver fiber module
broadcom corporation p.o. box 57013 16215 alton parkway irvine, ca 92619-7013 ? 2002 by broadcom corporation all rights reserved printed in the u.s.a. broadcom ? and the pulse logo are trademarks of broadcom corporat ion and/or its subsidiaries in the united states and certain other countries. all other trademarks are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass trans portation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as-is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement. r evision h istory revision date change description al2100-ds01-405-r 11/11/02 first revision AL2100-DS00-R 2/22/02 initial release
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r table of contents page i t able of c ontents section 1: overview ............................................................................................................. 1 section 2: pin descriptions ................................................................................................ 2 section 3: functional description ...................................................................................... 5 100base-tx to 100base-fx conversion .................................................................................................... 5 100base-fx to 100base-tx conversion .................................................................................................... 5 full duplex application ............................................................................................................................... 5 elastic store ............................................................................................................................... .................. 5 fault propagation ............................................................................................................................... .......... 6 fiber-to-fiber ................................................................................................................. ......................... 6 fiber-to-twisted pair.......................................................................................................... ..................... 6 twisted pair-to-fiber.......................................................................................................... ..................... 6 redundant function............................................................................................................. ................... 7 redundant link ................................................................................................................. ...................... 8 receive link fault ............................................................................................................. ..................... 8 transmits link fault........................................................................................................... ..................... 8 led indicators ................................................................................................................. ....................... 9 led configuration ............................................................................................................................... ...... 10 serial management interface .................................................................................................................... 10 phy addresses.................................................................................................................. ................... 10 clock source................................................................................................................... ...................... 10 power source ................................................................................................................... .................... 11 100base-twisted pair phy ........................................................................................................................ 11 general description ............................................................................................................ .................. 11 encoder/decoder ................................................................................................................ .................. 11 link monitor ................................................................................................................... ....................... 11 auto-negotiation/auto-negotiation selection.................................................................................... .... 11 analog adaptive equalizer...................................................................................................... .............. 12 clock recovery ................................................................................................................. .................... 12 baseline wander correction ..................................................................................................... ............ 13 multi mode transmitter ......................................................................................................... ................ 13 stream cipher scrambler/descrambler ............................................................................................ .... 13
al2100 preliminary data sheet 11/11/02 broadcom corporation page ii table of contents document al2100-ds01-405-r hp-auto mdi/mdix ............................................................................................................... ................13 100base fiber phy ............................................................................................................................... ......14 encoder/decoder................................................................................................................ ...................14 link monitor ................................................................................................................... ........................14 clock recovery ................................................................................................................. ....................14 transmitter .................................................................................................................... ........................14 far end fault (fef)............................................................................................................ ...................14 transmit driver ................................................................................................................ ......................15 section 4: register descriptions ..................................................................................... 16 100base-tx phy registers ........................................................................................................................16 control register............................................................................................................... ......................17 status register ................................................................................................................ ......................17 phy identifier 1 register ...................................................................................................... .................18 phy identifier 2 register ...................................................................................................... .................18 auto-negotiation advertisement register ........................................................................................ .....19 auto-negotiation link partner ability register/link partner next page message.................................19 auto-negotiation expansion register............................................................................................ ........20 auto-negotiation next page transmit register................................................................................... ..20 diagnostic register ............................................................................................................ ...................21 power/loopback register ........................................................................................................ .............21 cable measurement capability register .......................................................................................... .....21 receive error counter.......................................................................................................... .................22 power management register ...................................................................................................... ..........22 operation mode register ........................................................................................................ ..............23 crc for recent received packet ................................................................................................. ........23 100base-fx phy registers ........................................................................................................................24 control register............................................................................................................... ......................24 status register ................................................................................................................ ......................25 phy identifier 1 register ...................................................................................................... .................25 phy identifier 2 register ...................................................................................................... .................26 receive error counter.......................................................................................................... .................26 power management register ...................................................................................................... ..........26 operation mode register ........................................................................................................ ..............27 crc for recent received packet ................................................................................................. ........27
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r table of contents page iii common registers ............................................................................................................................... ..... 27 mode control register .......................................................................................................... ................ 27 common register 1, 2, and 3 .................................................................................................... ........... 28 led blink rate register 4 ...................................................................................................... .............. 28 led0 setting1 register 5 ....................................................................................................... .............. 28 led0 setting2 register 6 ....................................................................................................... .............. 28 led1 setting1 register 7 ....................................................................................................... .............. 28 led1 setting2 register 8 ....................................................................................................... .............. 29 led2 setting1 register 9 ....................................................................................................... .............. 29 led2 setting2 register 10 ...................................................................................................... ............. 29 led3 setting1 register 11 ...................................................................................................... ............. 30 led3 setting2 register 12 ...................................................................................................... ............. 30 led4 setting1 register 13 ...................................................................................................... ............. 30 led4 setting2 register 14 ...................................................................................................... ............. 30 section 5: 4b/5b code-group table ................................................................................ 31 section 6: smi read/write sequence ............................................................................... 32 section 7: electrical specifications ................................................................................. 33 absolute maximum ratings ...................................................................................................................... 33 recommended operating conditions ...................................................................................................... 33 electrical characteristics .......................................................................................................................... 33 section 8: timing and ac characteristics ...................................................................... 35 clock timing ............................................................................................................................... ................ 35 reset timing ............................................................................................................................... ................ 35 management data interface timing .......................................................................................................... 36 section 9: tx app lication termination ............................................................................ 37 section 10: fx appl ication termination .......................................................................... 38 section 11: power and ground filtering .........................................................................39 section 12: package dime nsions (48-pin tqfp) ............................................................ 40 section 13: thermal characteristics ................................................................................ 41 section 14: ordering information ..................................................................................... 42
al2100 preliminary data sheet 11/11/02 broadcom corporation page iv list of figures document al2100-ds01-405-r l ist of f igures figure 1: system block diagram ................................................................................................. ........................ i figure 2: al2100 pin out ....................................................................................................... ............................ 1 figure 3: state machine for redundant function ................................................................................. .............. 7 figure 4: redundant link....................................................................................................... ............................. 8 figure 5: reset timing......................................................................................................... .............................35 figure 6: management interface timing .......................................................................................... .................36 figure 7: tx application....................................................................................................... .............................37 figure 8: fx application....................................................................................................... .............................38 figure 9: power and ground filtering ........................................................................................... ....................39 figure 10: quad flat pack outline (7 x 7 mm) ................................................................................... ..............40
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r list of tables page v l ist of t ables table 1: pin descriptions...................................................................................................... .............................. 2 table 2: led formats ........................................................................................................... ............................. 9 table 3: events for led operation.............................................................................................. ..................... 10 table 4: spd100 0 settings ..................................................................................................... ........................ 12 table 5: registers 0 through 31 ................................................................................................ ....................... 16 table 6: register 0: control register bit description .......................................................................... ............. 17 table 7: register 1: status register bit description ........................................................................... ............. 17 table 8: register 2: phy identifier 1 register bit description ................................................................. ........ 18 table 9: register 3: phy identifier 2 register bit description ................................................................. ........ 18 table 10: register 4: auto-negotiation advertisement register bit description.............................................. 19 table 11: register 5: auto-negotiation link partner ability register/link partner next page message bit description .................................................................................................................... ................... 19 table 12: register 6: auto-negotiation expansion register bit description .................................................... 20 table 13: register 7: auto-negotiation next page transmit register bit description ..................................... 20 table 14: register 18: diagnostic register bit description..................................................................... ......... 21 table 15: register 19: power/loopback register bit description................................................................. ... 21 table 16: register 20: cable measurement capability register bit description ............................................. 21 table 17: register 21: receive error counter bit description ................................................................... ...... 22 table 18: register 22: power management register bit description .............................................................. 2 2 table 19: register 23: operation mode register bit description................................................................. .... 23 table 20: register 24: crc for recent received packet bit description........................................................ 23 table 21: 100base-fx phy registers ............................................................................................. ................ 24 table 22: register 0: control register bit description ......................................................................... ............ 24 table 23: register 1: status register bit description .......................................................................... ............ 25 table 24: register 2: phy identifier 1 register bit description ................................................................ ....... 25 table 25: register 3: phy identifier 2 register bit description ................................................................ ....... 26 table 26: register 21: receive error counter bit description ................................................................... ...... 26 table 27: register 22: power management register bit description .............................................................. 2 6 table 28: register 23: operation mode register bit description................................................................. .... 27 table 29: register 24: crc for recent received packet bit description........................................................ 27 table 30: common register 0: mode control register (map to tp_phy, reg. 28) bit description ............... 27 table 31: common register 4: led blink rate (map to tp_phy, reg. 29, page 1 a28 [15:12] = 0001) bit description .................................................................................................................... ................... 28
al2100 preliminary data sheet 11/11/02 broadcom corporation page vi list of tables document al2100-ds01-405-r table 32: common register 5: led0 setting1 (map to tp_phy, reg 30, page 1 a28[15:12] = 0001) bit description .................................................................................................................... ....................28 table 33: common register 6: led0 setting2 (map to tp_phy, reg. 31, page 1 a28 [15:12] = 0001) bit description .................................................................................................................... ....................28 table 34: common register 7: led1 setting1 (map to tp_phy, reg. 29, page 2 a28 [15:12] = 0010) bit description .................................................................................................................... ....................28 table 35: common register 8: led1 setting2 (map to tp_phy, reg. 30, page 2 a28 [15:12] = 0010) bit description .................................................................................................................... ....................29 table 36: common register 9: led2 setting1 (map to tp_phy, reg. 31, page 2 a28 [15:12] = 0010) bit description .................................................................................................................... ....................29 table 37: common register 10: led2 setting2 (map to tp_phy, reg. 29, page 3 a28 [15:12] = 0011) bit description .................................................................................................................... ....................29 table 38: common register 11: led3 setting1 (map to tp_phy, reg. 30, page 3 a28 [15:12] = 0011) bit description .................................................................................................................... ....................30 table 39: common register 12: led3 setting2 (map tp_phy, reg. 31, page 3 a28 [15:12] = 0011) bit description .................................................................................................................... ....................30 table 40: common register 13: led4 setting1 (map to tp_phy, reg 29, page 4 a28 [15:12] = 0100) bit description .................................................................................................................... ....................30 table 41: common register 14: led4 setting2 (map tp_phy, reg 30, page 4 a28[15:12] = 0100) bit description .................................................................................................................... ....................30 table 42: 4b/5b code-group table ............................................................................................... ..................31 table 43: smi read/write sequence .............................................................................................. .................32 table 44: absolute maximum ratings ............................................................................................. .................33 table 45: recommended operating conditions ..................................................................................... ..........33 table 46: electrical characteristics........................................................................................... ........................33 table 47: clock timing ......................................................................................................... ............................35 table 48: reset timing ......................................................................................................... ............................35 table 49: management interface timing .......................................................................................... ................36 table 50: thermal characteristics .............................................................................................. ......................41 table 51: maximum junction temperature ......................................................................................... .............41
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r page 1 section 1: overview the al2100 ( figure 2 ) contains a physical layer interface (phy) for 100base-tx and a phy for 100base-fx networks. the phy contains all the necessary functions such as elastic store, quantizer, and driver circuits to complete a media converter design. the device converts the mlt3 scrambled sy mbols from the twisted-pair (tp) input port into 4b5b nrzi encoded data, and transmits it over fiber media. the 4b5b nrzi encoded data from the fiber-input port is converted to a scrambled mlt3 symbol stream for tp transmission. the device also supports far-end fault detection (fiber-only) and link status propagation. if any port is in a link-fail state, the device ceases to transmit data, and disables the appropriate output port. the device is transparent in regard to the connecting links. the media converter uses an elastic store to retime the received signal. the al2100 supports redundant link applications. a redundant link can be formed by either a switch with a 100base-fx transceiver that supports far-end fault signaling or two al2100s. in the event of a link failure, the redundant link is establi shed automatically. figure 2: al2100 pin out 30 31 32 33 34 35 36 25 26 27 28 29 al2100 1 2 3 4 5 6 7 8 9 10 11 12 xin txp txn gnd rbiad gnd sd_a/fxen_a rxp rxn vcc vccpll gnd vcc 13 14 15 16 17 18 19 20 21 22 23 24 redun# data_off reserved vcc phyad0/led_tp_sd led0 led1 led2/duplex led3/anen pdown# tp2fx_dis gnd 37 38 39 40 41 42 43 44 45 46 47 48 phyad4/fx_dis phyad1/led_fx_sd rst# xi xo gnd gnd phyad3/led4_fdx phyad2 mdc mdio vcc fip fin gnd iso vcc gnd vcc sd_bf/xen_b fop fon fef_dis fx2tp_dis 48tqfp_7x7mm
al2100 preliminary data sheet 11/11/02 broadcom corporation page 2 document al2100-ds01-405-r section 2: pin descriptions signal types: p = power pin g = ground pin ai = analog input pin ao = analog output pin d = digital pull-down pin u = digital pull-up pin overline = active low b = bi-directional digital pin table 1: pin descriptions name number type description vcc 1 p 2.5v supply. fip 2 ai fx pecl input + fin 3 ai fx pecl input - sd_b/fxen_b 4 ai sd_b/fxen_b: multilevel threshold input. when the input level is 0v, the fx module is disabled. when the input is > 1v, the fx module is enabled, and this pin is used as the sd input with the pecl threshold. fop 5 ao fx pecl output + fon 6 ao fx pecl output - gndfx 7 g ground. gnd 7 g ground. iso 8 bd iso (reset-read input): pull high to isolate the tp phy. gnd 9 g digital ground. vcc 10 p 2.5v supply. fef_dis/reserved 11 bd fef_dis (reset-read input): pull high to disable the remote fault function in the fiber phy, i.e. fiber-to-fiber fault propagation disable. output function is reserved. fx2tp_dis/reserved 12 bd fx2tp_dis (reset read input): pull high to disable fiber-to-twisted-pair fault propagation. output function is reserved. redun /reserved 13 bd redun : redundancy function input. input low to activate the chip; input high to put the chip in backup mode. for the primary chip, this pin is pulled low. for the secondary chip, this pin is connected to the data_off pin of the primary chip. output function is reserved. reserved/data_off 14 bd input function is reserved. data_off: (output) high to put the secondary chip in backup mode. for the primary chip, this pin is connected to the redun of the secondary chip. tp2fx_dis/reserved 15 bd tp2fx_dis (reset read input): pull high to disable twisted pair-to-fiber fault propagation. output function is reserved. reserved 16 bd input function is reserved. this pin is always pulled low. gnd 17 g ground.
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r page 3 vcc 18 p 2.5v supply. phyad0/ led_tp_sd 19 bu phyad0 (reset read input): pull high or low to set the phy address bit 0 for serial management function. led_tp_sd (output): indicates energy is detected on the twisted-pair input. the active level is the invert of the reset read value. led0 20 bu pull this pin high. led0 (output): low active. the default behavior blinks when the twisted- pair port detects receive activity. led1 21 bu pull this pin high. led1 (output): low active. the default behavior is on when the twisted- pair port in link-up condition. duplex/led2 22 bu duplex (reset read input): sets the duplex capability for twisted-pair port auto-negotiation function. led2 (output): the active value is the invert of the duplex input level. the default behavior blinks when the fiber port detects receive activity. anen/led3 23 bu anen (reset read input): auto-negotiation enable for the twisted pair port. led3 (output): the active value is the invert of the anen input level. the default behavior is on when the link-up condition is detected on the fiber port, and blinks when the remote fault condition is detected on the fiber port. pdown 24 iu pdown (low active input): pull low to put both tp and fiber ports into power-down mode. this is a regular input, not a reset read signal. vcc 25 p 2.5v supply. rxn 26 a receive ? for tp port in mdi mode. transmit ? for tp port in mdix mode. rxp 27 a receive + for tp port in mdi mode. transmit + for tp port in mdix mode. sd_a/fxen_a 28 ai sd_a/fxen_a: (multithreshold input): pull low to disable the fx function on the twisted pair (tp) port. pecl input level to enable the fx function of the tp port. pecl high level to indicate the signal detect from the connected fiber module. gnd 29 g ground. gnd 30 g ground. rbiad 31 a bias resister connection. connect to a 10k 1% resister to gnd vccpll 32 p vcc for analog bias, pll modules. gnd 33 g ground for transmit circuit. txn 34 a transmit ? in mdi mode. receive ? in mdix mode. txp 35 a transmit + in mdi mode. receive + in mdix mode. vcc 36 p 2.5v supply. gnd 37 g ground gnd 38 g ground xo 39 ao xo (output): crystal output. xi 40 ai xi (input): crystal input. xi and xo pins are designed to connect to a 25 mhz, 50-ppm crystal. when using an oscillator, connect the xi pin to the oscillator, and leave the xo pin unconnected. vcc 41 p 2.5v supply. rst 42 iu reset input is active low. table 1: pin descriptions name number type description
al2100 preliminary data sheet 11/11/02 broadcom corporation page 4 document al2100-ds01-405-r mdio 43 bu mdio (input/output): management data i/o. this serial input/output pin is used to read from and write to the mii register. the data value on the mdio pin is valid, and latched on the rising edge of mdc. this pin requires a 1 k ohm resistor pull-up. mdc 44 bd mdc (input): management data clock. the mdc clock input must be provided to allow serial management functions. this pin has a schmtt- trigger input. phyad1/led_fx_sd 45 bd phyad1 (reset-read input): pull high or low to set phy address bit 1 for serial management functions. led_fx_sd (output): led output for fiber signal detects. the active level is the invert of the reset read value. phyad2/reserved 46 bd phyad2 (reset-read input): pull high or low to set phy address bit 2 for serial management functions. output function is reserved. phyad3/led4_fdx 47 bd phyad3 (reset-read input): pull high or low to set phy address bit 3 for serial management functions. led4_fdx (output): the default behavior is on when the result of the auto-negotiation on the twisted pair port is full duplex. this led pin is fully programmable. the active level is the invert of the reset read value. phyad4/fx_dis 48 bd phyad4 (reset-read input): pull high or low to set phy address bit 4 for serial management functions. fx_dis (output): disable fiber output. the active level is the invert of the reset read value. table 1: pin descriptions name number type description
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100b ase-tx to 100base-fx conversion page 5 section 3: functional description the al2100 contains a physical layer interface (phy) for 100base-tx, and a phy for 100base-fx networks. the phy contains all the necessary functions, such as elastic store, quantizer, and driver circuits, to complete a media converter design. the device converts the mlt3 scrambled symbols from the twisted-pair (tp) input port into 4b5b nrzi encoded data, and transmits it over the fiber media. the 4b5b nrzi encoded data from the fiber-input port is converted to a scrambled mlt3 symbol stream for tp transmission. the device also supports far-end fault detection (fiber-only), and links status propagation. if any port is in a link-fail stat e, the device cease transmitting data, and disables the appropriate output port. in essence, the device is transparent in regard to the connecting links. the media converter uses an elastic store to retime the received signal. the al2100 supports redundant link applications. a redundant link can be formed by either a switch with the 100base-fx transceiver that supports far-end fault signaling or two al2100s. in the event of a link failure, the redundant link is automatically established. 100b ase -tx to 100b ase -fx c onversion the al2100's 100base-tx receiver receives the scramble mlt3 signals, and passes them to the clock recovery circuit for data/clock extraction.the device de-scrambles the signals, and decodes them into an nrz data stream. the signal is then passed through elastic-store circuitry for retiming. the resulting signal is converted into a serial nrzi data stream, and sent to the 100base-fx transmitter. 100b ase -fx to 100b ase -tx c onversion the al2100's 100base-fx receiver receives the nrzi data stream through the pecl receiver inputs, and passes them on to the clock recovery circuit for data/clock extraction. the device feeds the signals through elastic-store circuitry for retim ing and encoding the nrzi data, and conversion to scramble mlt3 signals. the signals are sent to the 100base-tx transmitter. f ull d uplex a pplication the ideal function of a media converter chip provides a full-duplex transparent media link. the al2100 supports full ieee 802.3-compliant auto-negotiation functions. auto-negotiation can be enabled to negotiate with the link partner for full- duplex applications. e lastic s tore the al2100 provides an on-chip elastic store. with the elastic store in place, the device retimes the received signal, and removes jitter. in order to reduce the latency, preambles are inserted to the packet.
al2100 preliminary data sheet 11/11/02 broadcom corporation page 6 fault propagation document al2100-ds01-405-r f ault p ropagation three types of fault propagation are provided using the following logic: tp_rcvr_active = wait_for_link || tp_link_up; tp_output_en = (fx_link_up || fx2tp_dis) && data_enable; fx_output_en = tp_rcvr_active || tp2fx_dis; f iber - to -f iber this is the same as the remote fault function. when remote fault is disabled, the al2100 disables the fx transmission if the received sd fails. f iber - to -t wisted p air this operation can be controlled via the fx2tp_dis signal. this signal is only defined in al2100 normal operation mode, not in rmii testing mode. this is a reset read signal. when this type of fault propagation is enabled, the failure of the fx link shuts down the twisted pair output. t wisted p air - to -f iber this operation is controlled via the tp2fx_dis signal. this signal is only defined in al2100 normal operation mode. this is a reset read signal. when this type of fault propagation is enabled, the absence of receiving energy shuts down the fiber transmission to inform the fiber link partner about the link failure. the al2100 propagates idle signals from media-to-media. after reception of the idle signal (all ones), the device transmits an idle signal to the opposite ports, i.e. tp-to-fiber or fiber-t o-tp. there are two types of link failure?receive or remote fault? also known as far-end fault. tp receive link failure in the event of a tp-receive-link failure, the al2100 ceases to transmit an idle signal to the fiber-optic driver. a valid tp l ink signal can be either a 10base-t link pulse or a 100base-tx idle signal. fiber receive link failure in the event of a fiber-receive-link failure, the al2100 ceases to transmit an idle signal to the tp driver, and puts the drive r into high-impedance mode. the device also sends a remote fault signal to the fiber-optic driver in addition to de-asserting the data_off signal. tp transmit link failure in the event of a tp transmit link failure, the tp far-end tran sceiver ceases to transmit an idle signal, and starts transmitti ng flp to the al2100. because the al2100 does not understand flp, it continues to transmit an idle signal to the fiber-optic driver.
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r fault propagation page 7 fiber transmit link failure in the event of a fiber-transmit-link failure, the far-end transceiver, with remote fault signaling capability, transmits the r f signal to the al2100. as a result, the al2100 performs two tasks: ceases to transmit an idle signal to the tp driver, and puts the driver into high-impedance mode,de-asserting the data_off signal. r edundant f unction fault_out = data_enable && !fx_link; the logic above uses the tp_rcvr_active signal to gate the fx output. when the tp receiver is disconnected, it forces the fx side to drop the link, and causes the tp at the remote side to drop the link as well. when both sides receive activity in the tp side, the fx port on each side is enabled, and the link-up occurs. the link status of the fx port enables the tp output, and causes them to link up. the fx remote fault condition is generated by the standard fef_detect state machine. three timers generate the tp_rcvr_active signal. the first one is the activity_timer; the second one is the link_up_timer; the third is the tx_disable_timer. when using the activity_timer to determine whether there is a signal on the wire, start the link_up_timer, and wait for the an to complete. if the link_up_timer expires, start the tx_disable_timer, and disable fx_ouput_en and tx_output_en for a predefined period of time. see figure 3 for more details. figure 3: state machine for redundant function tp_quite wait_ for_link start link_up_timer link_disable start tx_disable_timer tp_link_up idle activity_timer _reset link_up_timer_done && !tp_link_up || activity_timer_done tp_link_up !tp_link_up !activity_timer_done tx_disable_timer_done reset link_pulse || sigdet
al2100 preliminary data sheet 11/11/02 broadcom corporation page 8 fault propagation document al2100-ds01-405-r r edundant l ink the al2100 supports redundant links through the use of the data_off and redun signals. the redundant link function is only available for the fiber port. an implementation of a redundant link is shown in figure 4 . the redundant link can also be configured with two fiber switch-ports, a far-end fault signaling support required, and two al2100s. there are two scenarios: either redundant link transmits a lin k fault or the receive link fault triggers the redundant link. figure 4: redundant link r eceive l ink f ault in the event of a receive-link failure, the receiver goes into a link-down mode. the al2100 takes the following actions: starts transmitting the remote fault signal puts the txp and txn pins in high-impedance mode de-asserts the data_off signal the far-end primary transceiver is normally in a link-up state, and a back-up transceiver is in a link-fail state. during recei ve- link failure, the local al2100 enables data transmission of the backup transceiver by asserting the redun signal. the backup al2100 starts sending copies of the transmit signal. the primary far-end receiver that receives the rf signal enters the link-fail state. the back-up transceiv er exits the link-fail state upon receiving a signal from the local al2100, re- establishing the link. when the primary link is repaired, the redun is de-asserted. t ransmits l ink f ault the 100base-fx specification provides a way to detect a transmit-link failure. whenever a fiber receiver experiences a receive-link failure, it transmits a far-end fault signal. the far-end fault signal is indicated by the far-end fault idle sign al (84 local primary al2100 primary data_off far end back up al2100 far end primary al2100 transformer transformer redun# data_off local back up al2100 redun# redundant link back up redun redun
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r fault propagation page 9 ones followed by a zero). when the al2100 receives the far-end fault signal, it is notified by the far-end station that a transmit-fault occurred. the device goes into a link-down state, and takes the following actions: puts the txp and txn pins in high-impedance mode de-asserts the data_off signal the data transmission is assumed by the backup al2100, and starts sending copies of the signals. upon re-establishment of the primary fiber, data_off is asserted, and the backup data link is turned off. led i ndicators led output all the led pins in the al2100 are mult ifunction i/os. their input is used in the reset-read operation for the secondary definition. all led pins have internal pull-ups. the on output value depends on the reset-read value of the led pin. when the reset-read value is high, the default for all led pins, the on output value is low. when the reset read value is low, the on output value is high. default led formats are given in table 2 . these leds can be configured into different modes. to configure the leds to work with other operation mode other than default mode, see ?led configuration? on page 10 . the al2100 also support the following leds: led4_fdx: default defined as full-duplex of auto-negotiation resulting on the tp port. led_fx_sd: signal detects on fiber phy. this led set by hardware pin 45 cannot be programmable. led_tx_sd: receiving energy detects on the tp port. this led is set by hardware pin 19, and cannot be programmable table 2: led formats led format led0 rxact_tp (blink) led1 link_tp (on) led2 rxact_fx (blink) led3 link_fx (on) / remote_fault (blink) led4 duplex_tp (on) note led connections and the source/sink current depend on the default setting.
al2100 preliminary data sheet 11/11/02 broadcom corporation page 10 serial management interface document al2100-ds01-405-r led c onfiguration the led interface is fully configurable via the common register setting. see table 3 . each led has two 16-bit registers that define the operation. see ?common registers? on page 27 for details. s erial m anagement i nterface mii management access is performed via pin mdc and mdio. the mdc input pin is schmtt triggered to avoid noise on this bused signal. the phy?s internal registers are accessible only through the mii 2-wire serial management interface (smi). mdc is a clock input to the phy, which is used to latch in or out data and instructions for the phy. the clock can run at any speed from dc to 25 mhz. mdio is a bi-directional connection used to write instructions to, write data to, or read data from the phy. each data bit is latched either in or out on the rising edge of md c. mdc is not required to maintain any speed or duty cycle, provided no half cycle is less than 20 ns, and that data is presented synchronous to mdc. mdc and mdio are a common signal pair to all phys on a design. therefore, each phy must have its own unique physical address. the physical address of the phy is set by using the pins defined as phyad[4:0]. these input signals are strapped externally, and sampled as reset is negated. at idle, the phy is responsible to pull the mdio line to a high state. therefore, a 1k ohm resistor is required to connect the mdio line to vcc. phy a ddresses two phy addresses are taken under al2100 mode. one is phyad [4:0], and the other is phyad [4:0] + 1. the first one is for twisted-pair phy; the second is for fiber phy. the phy addresses are set via the phyad4, phyad3, phyad2, phyad1, and phyad0 signals. c lock s ource the clock source for this chip is from the xi signal. in normal operation mode (media converter), the xi signal is connected to a 25 mhz, 50 ppm oscillator or xi and xo signals are connected to a 25 mhz, 50 ppm crystal. table 3: events for led operation bit events description 7rxact_fx 6link_fx 5link_tp 4 duplex_tp 3txact_tp 2 remote_fault 1n/a 0rxact_tp
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100base- twisted pair phy page 11 p ower s ource a single 2.5 v is supplied for all digital and analog operations. 100b ase -t wisted p air phy g eneral d escription the twisted pair phy performs all of the physical layer interface functions for 100base-tx full or half-duplex on cat5 twisted pair cable. the 100base-tx phy performs encoder/decoder, link monitor, auto-negotiation selection, adaptive equalization, clock/data recovery, baseline wander correction, multimode tr ansmitter, scrambler/descrambl er, far-end fault (fef), and auto-mdi/mdix. it is fully compliant with the ieee 802.3 and 803.3u standards. e ncoder /d ecoder in 100base-tx mode, the al2100 transmits and receives data streams on twisted pair. when the mii transmit enable is asserted, nibble wide (4-bit) data from the transmit data pins is encoded into 5-bit code groups, and inserted into the transmi t data stream. the 4b5b encoding is shown in the 4b/5b code-group table. the transmit packet is encapsulated by replacing the first two nibbles of preamble with a start- of-stream delimiter (j/k c odes), and appending an end-of-stream delimiter (t/r codes) to the end of packet. when the mii transmit error input is asserted during a packet, the error code group (h) is sent in place of the corresponding data code group. the transmitter repeatedly sends the idle code group between packets. in 100base-tx mode, the encode data stream is scrambled by a stream cipher block, and serialized and encoded into the mlt3 signal level. a multimode transmit dac (digital to analog converter) is used to drive the mlt3 data onto twisted pair cable. following are baseline wander correction, adaptive equalization, and clock/data recovery in 100base-tx mode. the receive data stream is converted from mlt3 to serial nrz data. the nrz data is descrambled by the stream cipher block, and deserialized and aligned into 5-bit code groups. l ink m onitor in 100base-tx mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. the signal levels are qualified using squelch detect circuits. when no signal, or a certain valid signal, is detected on the receiv e pair for a minimum period of time, the link monitor enters th e link-pass state, and the transmit and receive functions are enabled. a uto -n egotiation /a uto -n egotiation s election auto-negotiation selection is on the 100base-t twisted-pair phy only; it is not operating in 100base-fiber phy. in 100base-tx mode, auto-negotiation can be enabled or di sabled by hardware or software control. when the auto- negotiation function is enabled, the 100base-tx phy automatically chooses its mode of operation by advertising its abilities, and comparing them with those received from its link part ner. the 100base-tx phy can be configured to advertise as 100base-tx full-duplex or 100basetx half-duplex. the default auto-negotiation mode is configured via a reset read value of led3/anen, led2/duplex. the spd100 signal is always defaulted to 1. when the spd100 is set to 0, it is undefined, and the result is unexpected.
al2100 preliminary data sheet 11/11/02 broadcom corporation page 12 100base-twisted pair phy document al2100-ds01-405-r a nalog a daptive e qualizer the analog adaptive equalizer removes inter-symbol interference (isi) created by the transmission channel media. the phy is designed to accommodate a maximum of 140 meters utp cat-5 cable. an at&t 1061 cat-5 cable of this length typically has an attenuation of 31db at 100 mhz. a typical attenuation of 100-meter cable is 21db. the worst case cable attenuation is around 24-26db, as defined by tp-pmd specification. the amplitude and phase distortion from the cable cause isi, which makes clock and data recovery difficult. the adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable. the equalizer has the ability to change its equalizer frequency response according to cable length. the equalizer tunes itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable. c lock r ecovery the equalized mlt-3 signal passes through the slicer circuit, and gets converted to nrzi format. the phy uses a proprietary mixed-signal phase locked loop (pll) to extract clock information from the incoming nrzi data. the extracted clock is used to retime the data stream, and set the data boundaries. the transmit clock is locked to the 25 mhz clock input, while the receive clock is locked to the incoming data streams. when initial lock is achieved, the pll switches to the data stream, extracts the 125 mhz clock, and uses it for bit framing for the recovered data. the recovered 125 mhz clock is also used to generate the 25 mhz rx_clk signal. the pll requires no external components for its operation, and has high noise immunity and low jitter. it provides fast phase alignment, and locks to data in one transition. its data/clock acquisition time after power-on is less than 60 transitions. the pll can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. when no valid data is present, i.e. when the sd is de-asserted, the pll switches and locks onto tx_clk. this provides a continuously running rx_clk. at the pcs interface, the 5-bit data rxd[4:0] is synchronized to the 25 mhz rx_clk. table 4: spd100 0 settings register and bit name description register 0, bit 13 speed select 1 = 100mbps set to 1 for normal operation. 0 is prohibited. register 0, bit 12 anen enable 1 = enable auto-negotiation 0 = disable auto-negotiation register 0, bit 8 duplex the default value is !anen && duplex register 4, bit 8 / register 1, bit 14 100base-tx full duplex the default value of this bit is duplex register 4, bit 7 / register 1, bit 13 100base-tx the default value of this bit is anen ||!duplex
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100base- twisted pair phy page 13 b aseline w ander c orrection a 100base-tx data stream is not always dc balanced because the receive signal must pass through a transformer. the dc offset of the differential receive input can wander. this effect, known as baseline wander, can greatly reduce the noise immunity of the receiver. the 100base-tx phy automatically compensates for baseline wander by removing the dc offset from the input signal, and thereby significantly reduces the chance of a receive symbol error. m ulti mode t ransmitter the multimode transmitter transmits mlt3 coded symbols in 100base-tx mode, nrzi coded symbols in 100base-fx mode. it uses a current drive output, which is well balanced, and produces very low noise transmit signals. pecl voltage levels are produced with resistive terminations in 100base-fx mode. s tream c ipher s crambler /d escrambler in 100base-tx mode, the transmit data stream is scrambled to reduce radiated emissions on the twisted pair cable. the data is scrambled by exclusive oring the nrz signal with the output of an 11-bit wide linear feed back shift register (lfsr), which produces a 2047-bit non repeating sequence. the scrambler reduces peak emission by randomly spreading the signal energy over the transmit frequency range, and eliminating peaks at certain frequencies. the receiver descrambles the incoming data stream by ex clusive oring it with the same sequence generated at the transmitter. the descrambler detects the state of transmit lfsr by looking for a sequence representing consecutive idle codes. the descrambler locks to the scrambler state after detecting a sufficient number of consecutive idle code groups. the receiver does not attempt to decode the data stream unless the descrambler is locked. when locked, the descrambler continuously monitors the data stream to make sure that it has not lost synchronization. the receive data stream is expected to contain interpacket idle periods. if the descrambler does not detect enough idle code within 724 s, it becomes unlocked, and the receive decoder is disabled. the descrambler is always forced into the unlock state when a link failure condition is detected. hp-a uto mdi/mdix this feature detects the required cable connection type straight through or crossed over, and makes corrections automatically. note the baseline wander circuit is not required in 100base-fx phy. note the stream cipher descrambler is not used in the 100base-fx mode.
al2100 preliminary data sheet 11/11/02 broadcom corporation page 14 100base fiber phy document al2100-ds01-405-r 100b ase f iber phy the al2100 includes a fiber phy. it can transmit and receive data over fiber-optic cable when paired with an external fiber- optic line driver and receiver. in fx mode, the receive data stream differential pecl level is sampled from the fiber-optic receiver. nrzi decoding is used instead of mlt3. baseline wander, adaptive equalization, and stream cipher descrambler functions are bypassed. e ncoder /d ecoder . the decoded data is driven onto the mii receive data pins. when an invalid code group is detected in the data stream, the fiber phy asserts the mii rxer signal. the fiber phy also asserts rxer for several other error conditions that improperly terminate the data stream. while rxer is asserted, the receive data pins are driven with 4-bit code, indicating the type of error detected. the error codes are listed in table 42 on page 31 . l ink m onitor in 100base-fx mode, the external fiber-optic receiver performs the signal energy detection function, and communicates this information directly to the sd signal, pin 4. c lock r ecovery the digital clock recovery creates all internal transmit and receive clocks. the transmit clock is locked to the 25 mhz clock input, while the receive clock is lock to the incoming data stream. the clock recovery circuit optimized to mlt3, nrzi. the input data stream is sampled by the recovery clock, and fed synchronously to the adaptive equalizer. t ransmitter serialized data bypasses the scrambler and 4b/5b encoder in fx mode. the output data is from the nrzi pecl signals. the pecl level signals are used to drive the fiber-transmitter. f ar e nd f ault (fef) auto-negotiation provides the mechanism to inform the link par tner that a remote fault has occurred. however, auto- negotiation is disabled in 100base-fx applications. an alter native in-band signaling function (fefi) is used to signal a remote fault condition. fefi is a stream of 84 consecutive 1s followed by one logic 0. this pattern is repeated three times. a fefi signals only under the following conditions: when no activity is received from the link partner when the clock recovery circuit detects a signal error or pll lock error when the management entity sets the transmit fef bit
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100b ase fiber phy page 15 t ransmit d river the transmit driver does not perform filtering. it uses a current drive output, which is well balanced, and produces a low nois e pecl signal. pecl voltage levels are produced with resistive terminations.
al2100 preliminary data sheet 11/11/02 broadcom corporation page 16 100base-tx phy registers document al2100-ds01-405-r section 4: register descriptions the first seven registers of the mii register set are defined by the mii specification. in addition to these required registers are several altima communications, inc. specific registers. there are reserved registers and/or bits that are for altima internal use only. the following standard registers are supported. legend: rw = read and write access sc = self-clearing ll = latch low until cleared by reading ro = read-only rc = cleared on read lh = latch high until cleared by reading 100 base -t x phy r egisters note register numbers are in decimal format. the values are in hexadecimal (h) or binary format. when writing to registers, it is recommended that a read/modify/write operation be performed because unintended bits can get set to unwanted states. this applies to all registers, including those with reserved bits. table 5: registers 0 through 31 register description default 0 control register 3000 1 status register 6049 2 phy identifier 1 register 0022 3 phy identifier 2 register 5521 4 auto-negotiation advertisement register 0181 5 auto-negotiation link partner ability register 41e1 6 auto-negotiation expansion register 0005 7 next page advertisement register 2801 8-15 reserved xxxx 16 interrupt level control register 1800 17 interrupt control/status register is reserved because there is no hardware support. 0000 18,19 reserved xxxx 20 cable measurement capability register xxxx 21 receive error counter register 0000 22-31 reserved xxxx
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100base-tx phy registers page 17 c ontrol r egister s tatus r egister table 6: register 0: control register bit description bit name description mode default 15 reset 1 = phy reset. this bit is self-clearing. rw/sc 0 14 loop back 1 = enable loopback mode. this loops back txd to rxd, and ignores all activity on the cable media. 0 = normal operation. rw 0 13 speed select set to 1 for normal operation; 0 is prohibited. rw 1 12 anen enable 1 = enable auto-negotiation process (overrides 0.13 and 0.8) 0 = disable auto-negotiation process. mode selection is controlled via bit 0.8, 0.13 or through the mode pins. rw set by anen 11 power down 1 = power-down all blocks. while in the power-down state, the phy responds to management transactions. setting pdown , pin 24, to low has the same result. 0 = normal operation. rw 0 10 isolate 1 = electrically isolate the phy from mii. phy still responds to smi. 0 = normal operation. rw 0 9 restart anen 1 = restart auto-negotiation process. 0 = normal operation. rw/sc 0 8 duplex mode 1 = full duplex. 0 = half duplex. rw set by a mode pin 7 collision test 1 = enable collision test, which issues the col signal in response to the assertion of the tx_en signal. collision test is disabled when the pcsbp pin is high. collision test is enabled regardless of the duplex mode. 0 = disable col test. rw 0 6:0 reserved rw 0000000 table 7: register 1: status register bit description bit name description mode default 15 100base-t4 permanently tied to 0 indicates no 100baset4 capability. ro 0 14 100base-tx full duplex 1 = 100basetx full-duplex capable. 0 = not 100basetx full-duplex capable. ro set by duplex pin 13 100base-tx half duplex 1 = 100basetx half-duplex capable. 0 = not tx half-duplex capable. ro set by duplex pin 12 10base-t full duplex 1 = 10baset full-duplex capable. 0 = not 10baset-full duplex capable. ro 0 11 10base-t half duplex 1 = 10baset half-duplex capable. 0 = not 10baset half-duplex capable. ro 0 10:7 reserved ro 0000 6 mf preamble suppression the phy is able to perform management transactions without an mdio preamble. the management interface needs a minimum of 32 bits of preamble after reset. ro 1
al2100 preliminary data sheet 11/11/02 broadcom corporation page 18 100base-tx phy registers document al2100-ds01-405-r phy i dentifier 1 r egister phy i dentifier 2 r egister 5 anen complete 1 = auto-negotiation process completed. registers 4, 5, and 6 are valid after this bit is set. 0 = auto-negotiation process not complete. ro 0 4 remote fault 1 = remote fault condition detected. 0 = no remote fault. this bit remains set until it is cleared by reading register 1. ro/lh 0 3 anen ability 1 = able to perform auto-negotiation function; default value determined by anen pin. 0 = unable to perform auto-negotiation function. ro set by anen pin 2 link status 1 = link is established. if the link fails, this bit is cleared, and remains at 0 until the register is read again. 0 = link has gone down. ro/ll 0 1 jabber detect 1 = jabber condition detect. 0 = no jabber condition detected. ro/lh 0 0 extended capability 1 = extended register capable. this bit is tied permanently to 1. ro 1 table 8: register 2: phy identifier 1 register bit description bit name description mode default 15:0 oui composed of the third through the 18th bits of the organizationally unique identifier (oui), respectively. see note below. ro 0022(h) note based on an oui of 0010a9 (hex) table 9: register 3: phy identifier 2 register bit description bit name description mode default 15:10 oui assigned to the 19th through 24th bits of the oui. see note below. ro 010101 9:4 model number six bit manufacturer?s model number. ro 010010 3:0 revision number 4-bit manufacturer?s revision number. ro 0001 note based on an oui of 0010a9 (hex) table 7: register 1: status register bit description bit name description mode default
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100base-tx phy registers page 19 a uto -n egotiation a dvertisement r egister a uto -n egotiation l ink p artner a bility r egister /l ink p artner n ext p age m essage table 10: register 4: auto-negotiation advertisement register bit description bit name description mode default 15 next page 1 = next page enabled. 0 = next page disabled. rw 0 14 acknowledge this bit is set internally after receiving three consecutive and consistent flp bursts. ro 0 13:11 reserved 10 fdfc full-duplex flow control 1 = advertise that the dte (mac) has implemented both the optional mac control sublayer and the pause function as specified in clause 31 and annex 31b of 802.3u. 0 = mac does not support flow control. 9 100base-t4 technology not supported. this bit always 0 ro 0 8 100base-tx full duplex 1 = 100basetx full-duplex capable. 0 = not 100basetx full-duplex capable. rw set by duplex pin 7 100base-tx 1 = 100basetx half-duplex capable. 0 = not tx half-duplex capable. rw set by duplex pin 6 10base-t full duplex 1 = 10baset full-duplex capable. 0 = not 10baset full-duplex capable. rw 0 5 10base-t 1 = 10baset half-duplex capable. 0 = not 10baset half-duplex capable. rw 0 4:0 selector field protocol selection [00001] = ieee 802.3. ro 00001 table 11: register 5: auto-negotiation link partne r ability register/link partner next page message bit description bit name description mode default 15 next page 1 = link partner desires next page transfer. 0 = link partner does not desire next page transfer. ro 0 14 acknowledge 1 = link partner acknowledges reception of flp words. 0 = not acknowledged by link partner. ro 0 13:10 reserved 9 100base-t4 1 = 100baset4 supported by link partner. 0 = 100baset4 not supported by link partner. ro 0 8 100base-tx full duplex 1 = 100basetx full-duplex supported by link partner. 0 = 100basetx full-duplex not supported by link partner. ro 0 7 100base-tx 1 = 100basetx half-duplex supported by link partner. 0 = 100basetx half-duplex not supported by link partner. ro 0 6 10base-t full duplex 1 = 10mbps full-duplex supported by link partner. 0 = 10mbps full-duplex not supported by link partner. ro 0 5 10base-t 1 = 10mbps half-duplex supported by link partner. 0 = 10mbps half-duplex not supported by link partner. ro 0 4:0 selector field protocol selection [00001] = ieee 802.3. ro 00001
al2100 preliminary data sheet 11/11/02 broadcom corporation page 20 100base-tx phy registers document al2100-ds01-405-r a uto -n egotiation e xpansion r egister a uto -n egotiation n ext p age t ransmit r egister note when this register is used as next page message, the bit definition is the same as register 7. table 12: register 6: auto-negotiation expansion register bit description bit name description mode default 15:5 reserved ro 0 4 parallel detection fault 1 = fault detected by parallel detection logic. this fault is due to more than one technology detecting a concurrent link-up condition. this bit can only be cleared by reading register 6, using the management interface. 0 = no fault detected by parallel detection logic. ro/ lh 0 3 link partner next page able 1 = link partner supports next page function. 0 = link partner does not support next page function. ro 0 2 next page able next page is supported. ro 1 1 page received this bit is set when a new link code word has been received into the auto-negotiation link partner ability register. this bit is cleared upon a read of this register. rc 0 0 link partner anen-able 1 = link partner is auto-negotiation capable. 0 = link partner is not auto-negotiation capable. ro 0 table 13: register 7: auto-negotiation n ext page transmit register bit description bit name description mode default 15 np 1 = another next page desired. 0 = no other next page transfer desired. rw 0 14 reserved ro 0 13 mp 1 = message page. 0 = unformatted page. rw 1 12 ack2 1 = complies with message. 0 = does not comply with message. rw 0 11 tog_tx 1 = previous value of transmitted link code word equals 0. 0 = previous value of transmitted link code word equals 1. rw 0 10:0 code message/unformatted code field. rw
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100base-tx phy registers page 21 d iagnostic r egister p ower /l oopback r egister c able m easurement c apability r egister table 14: register 18: diagnostic register bit description bit name description mode default 15:13 reserved rw 0 12 force link pass tx 1 = enable force link at 100 base-t. 0 = disable. rw 0 11 dplx this bit indicates the result of the auto-negotiation for duplex. 1 = full duplex. 0 = half duplex. ro set by pin 10 speed this bit indicates the result of the auto-negotiation for speed. 1 = 100base-t. 0 = 10base-t. ro 1 9 rx_pass in 100bt mode, this bit indicates that the valid signal was received but not necessarily locked onto. ro 0 8 rx_lock this bit indicates that the receive pll has locked onto the received signal for the selected speed of operation (100base- tx). this bit is set whenever a cycle-slip occurs, and remains set until it is read. ro/rc 0 7:0 reserved ro 0 table 15: register 19: power/loopback register bit description bit name description mode default 14:7 reserved rw 00000000 6 reserved rw 0 5 disable watch dog timer for decipher 1 = disable watchdog timer. 0 = enable watchdog timer. rw 0 4low power mode disable 1= disable advance power saving mode. 0= enable advance power saving mode. rw 0 3 enable digital loopback 1 = enable digital loopback. 0 = disable digital loopback. rw 0 2 reserved reserved rw 0 1 reserved reserved. rw 0 0 reserved reserved. rw 0 table 16: register 20: cable measurement capability register bit description bit name description mode default 15 reserved rw 1 14 reserved 1 = turn on. 0 = turn off. rw 1 13:9 reserved ro 0
al2100 preliminary data sheet 11/11/02 broadcom corporation page 22 100base-tx phy registers document al2100-ds01-405-r r eceive e rror c ounter p ower m anagement r egister 8 adaptation disable 1 = turn on adaptation disable mode. 0 = turn off. to set the value of 20.7:4, turn on 20.8, and turn off 20.14, or this phy rejects to receive packets. rw 0 7:4 cable measurement capability these bits can be used as a cable length indicator. the bits are incremented from 0000 to 1111 with an increment of approximately 10 meters. the equivalent is 0 to 32db with an increment of 2db at 100 mhz. the value is a read back from the equalizer; the measured value is not absolute. rw x 3:0 reserved ro xxxx table 17: register 21: receive error counter bit description bit name description mode default 15:0 rx_er counter count receive error events. ro 0 table 18: register 22: power management register bit description bit name description mode default 15:14 reserved ro 00 13 pd_pll 1 = power down pll circuit. ro x 12 pd_equal 1 = power down equalizer circuit. ro x 11 pd_bt_rcvr 1 = power down 10 base t receiver. ro x 10 pd_lp 1 = power down link pulse receiver. ro x 9 pd_en_det 1 = power down energy detect circuit. ro x 8 pd_fx 1 = power down fx circuit. ro x 7:6 reserved rw 00 5 msk_pll 0 = force power up pll circuit. rw x 4 msk_equal 0 = force power up equalizer circuit. rw x 3 msk_bt_rcvr 0 = force power up 10 base t receiver. rw x 2 msk_lp 0 = force power up link pulse receiver. rw x 1 msk_en_det 0 = force power up energy detect circuit. rw x 0 msk_fx 0 = force power up fx circuit rw x table 16: register 20: cable measurement capability register bit description bit name description mode default
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100base-tx phy registers page 23 o peration m ode r egister crc for r ecent r eceived p acket table 19: register 23: operation mode register bit description bit name description mode default 15:14 reserved 13 reserved 12 reserved 11 scramble disable 1 = disable scrambler data. 0 = enable scrambler data. rw 0 10 reserved rw 0 9 pcsbp 1 = enable pcs bypass mode. 0 = disable pcs bypass mode. rw 0 23:8 reserved rw 0 7:6 reserved 5 reserved ro 0 4:0 reserved ro xxxxx table 20: register 24: crc for recent received packet bit description bit name description mode default 15:0 crc16 crc16 value displayed. for system level test purpose. rc 0000h
al2100 preliminary data sheet 11/11/02 broadcom corporation page 24 100base-tx phy registers document al2100-ds01-405-r 100b ase -fx phy r egisters c ontrol r egister table 21: 100base-fx phy registers register name address 0 control register 2100 1 status register 7849 2 phy identifier 1 register 0022 3 phy identifier 2 register 5523 4-20 reserved xxxx 21 receive error counter register 0000 22-31 reserved xxxx table 22: register 0: control register bit description bit name description mode default 15 reset 1 = phy reset. this bit is self-clearing. rw/sc 0 14 loopback 1 = enable loopback mode. this loops back txd to rxd, and ignores all the activity on the cable media. 0 = normal operation. rw 0 13 speed select 1 = 100mbps. default is always = 1. this bit set to 0 is undefined. rw 1 12 anen enable 1= n/a 0= disable auto-negotiation. this bit is always set to 0 in fx phy. rw 0 11 power down 1 = power down. all blocks except for smi are turned off. setting the pwrdn pin to high achieves the same result. 0 = normal operation. rw 0 10 isolate 1 = electrically isolate the phy from mii. phy is still able to response to smi. 0 = normal operation. rw 0 9restart anen 1 = restart auto-negotiation process. 0 = normal operation. rw/sc 0 8 duplex mode 1 = full duplex. 0 = half duplex. rw set by duplex pin 7 collision test 1 = enable collision test, which issues the col signal in response to the assertion of the tx_en signal. collision test is disabled when pcsbp pin is high. collision test is enabled regardless of the duplex mode. 0 = disable col test. rw 0 6:0 reserved rw 0000000
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r 100base-tx phy registers page 25 s tatus r egister phy i dentifier 1 r egister table 23: register 1: status register bit description bit name description mode default 15 100base-t4 permanently tied to 0 indicates no 100baset4 capability. ro 0 14 100base-tx full duplex 1 = 100basetx full-duplex capable. 0 = not 100basetx full-duplex capable. ro 1 13 100base-tx half duplex 1 = 100basetx half-duplex capable. 0 = not tx half-duplex capable. ro 1 12 10base-t full duplex 1 = 10baset full-duplex capable. 0 = not 10baset full-duplex capable. ro 0 11 10base-t half duplex 1 = 10baset half-duplex capable. 0 = not 10baset half-duplex capable. ro 0 10:7 reserved ro 0000 6 mf preamble suppression the phy is able to perform management transaction without mdio preamble. the management interface needs a minimum of 32 bits of preamble after reset. ro 1 5 anen complete 1 = auto-negotiation process completed. registers 4, 5, 6 are valid after this bit is set. 0 = auto-negotiation process not complete. ro 0 4 remote fault 1 = remote fault condition detected. 0 = no remote fault. this bit remains set until it is cleared by reading register 1. ro/lh 0 3 anen ability 1 = able to perform auto-negotiation function; default value determined by anen pin. 0 = unable to perform auto-negotiation function. ro 1 2 link status 1 = link is established. if link fails, this bit is cleared, and remains at 0 until register is read again. 0 = link has gone down. ro/ll 0 1 jabber detect 1 = jabber condition detect. 0 = no jabber condition detected. ro/lh 0 0 extended capability 1 = extended register capable. this bit is tied permanently to 1. ro 1 table 24: register 2: phy identifier 1 register bit description bit name description mode default 15:0 oui* composed of the third through 18th bits of the organizationally unique identifier (oui), respectively. ro 0022(h) note based on an oui is 0010a9 (hex).
al2100 preliminary data sheet 11/11/02 broadcom corporation page 26 100base-tx phy registers document al2100-ds01-405-r phy i dentifier 2 r egister r eceive e rror c ounter p ower m anagement r egister table 25: register 3: phy identifier 2 register bit description bit name description mode default 15:10 oui assigned to bits 19 through 24 of the oui. ro 010101 9:4 model number 6-bit manufacturer?s model number. ro 010010 3:0 revision number 4-bit manufacturer?s revision number. ro 0001 note based on an oui of 0010a9 (hex). when this register is used as next page message, the bit definition is the same as register 7. table 26: register 21: receive error counter bit description bit name description mode default 15:0 rx_er counter count receive error events. ro 0 table 27: register 22: power management register bit description bit name description mode default 15:14 reserved ro 00 13 pd_pll 1 = power down pll circuit. ro x 12 pd_equal 1 = power down equalizer circuit. ro x 11 reserved ro x 10 pd_lp 1 = power down link pulse receiver. ro x 9 pd_en_det 1 = power down energy detect circuit. ro x 8 pd_fx 1 = power down fx circuit. ro x 7:6 reserved rw 00 5 msk_pll 0 = force power up pll circuit. rw x 4 msk_equal 0 = force power up equalizer circuit. rw x 3 reserved rw x 2 msk_lp 0 = force power up link pulse receiver. rw x 1 msk_en_det 0 = force power up energy detect circuit. rw x 0 msk_fx 0 = force power up fx circuit. rw x
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r common registers page 27 o peration m ode r egister crc for r ecent r eceived p acket c ommon r egisters the following registers are mapped to registers 28 through 31 on the tp phy. register 28[15:12] is used as a page select. there are multiple pages of registers 29 through 31, depending on the value of register 28[15:12]. m ode c ontrol r egister table 28: register 23: operation mode register bit description bit name description mode default 15:14 reserved 13 clk_rclk_save 1 = set rclk save mode. rclk shuts off after 64 cycles of each packet. 0 12 reserved 11 scramble disable 1 = disable scrambler rw 1 10 reserved rw 0 9 pcsbp 1 = enable pcs bypass mode. rw 0 23:8 reserved rw 0 7:6 reserved 5 reserved ro 0 4:0 reserved ro xxxxx table 29: register 24: crc for recent received packet bit description bit name description mode default 15:0 crc16 crc16 value displayed. for system level test purposes. rc 0000h table 30: common register 0: mode control register (map to tp_phy, reg. 28) bit description a.28.15:12 page selection select multiple common register pages. rw 0000 a.28.11:7 reserved ro 0000 a.28.6 reserved ro 1 a.28.5 reserved ro 0 a.28.4 reserved ro 0 a.28.3 reserved rw 0 a.28.2 act select act event select. 0 = receive activity. 1 = tx or rx activity. rw 1 a.28.1 reserved ro 0 a.28.0 reserved ro 0
al2100 preliminary data sheet 11/11/02 broadcom corporation page 28 common registers document al2100-ds01-405-r c ommon r egister 1, 2, and 3 common registers 1, 2, and 3 are reserved. led b link r ate r egister 4 led0 s etting 1 r egister 5 the default operation for led0 is blink on tp rx_act. the default operation for led5 is blink when remote loopback packet is received. led0 s etting 2 r egister 6 led1 s etting 1 r egister 7 the default operation for led1 is on on tp_link. table 31: common register 4: led blink rate (map to tp_phy, reg. 29, page 1 a28 [15:12] = 0001) bit description bit name description mode default a1.29.15:8 reserved reserved ro 00000000 a1.29.7:0 blink rate set led blink rate. the blink rate is this number times 16 ms. default is 256 ms. rw 00010000 table 32: common register 5: led0 setting1 (map to tp_phy, reg 30, page 1 a28[15:12] = 0001) bit description bit name description mode default a1.30.15:13 reserved r 000 a1.30.12 force led on force led0 on. rw 0 a1.30.11:9 reserved r 000 a1.30.8 force led off force led0 off. rw 0 a1.30.7:0 msk blink blink mask. when the bits are set to 1, the corresponding event causes the led to blink. rw 00000001 table 33: common register 6: led0 setting2 (map to tp_phy, reg. 31, page 1 a28 [15:12] = 0001) bit description bit name description mode default a1.31.15:8 msk on on mask. when the bits are set to one, corresponding events cause the led to turn on. rw 00000000 a1.31.7:0 msk off off mask. when the bits are set to 1, corresponding events cause the led to turn off rw 00000000 table 34: common register 7: led1 setting1 (map to tp_phy, reg. 29, page 2 a28 [15:12] = 0010) bit description bit name description mode default a2.29.15:13 reserved reserved r 000 a2.29.12 force led on force led1 on. rw 0
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r common registers page 29 led1 s etting 2 r egister 8 led2 s etting 1 r egister 9 the default operation for led2 is blink on rxact_fx. led2 s etting 2 r egister 10 a2.29.11:9 reserved reserved r 000 a2.29.8 force led off force led1 off rw 0 a2.29.7:0 msk blink blink mask. when the bits are set to one, corresponding events cause the led to blink. rw 00000000 table 35: common register 8: led1 setting2 (map to tp_phy, reg. 30, page 2 a28 [15:12] = 0010) bit description bit name description mode default a2.30.15:8 msk on on mask. when the bits are set to 1, corresponding events cause the led to turn on. rw 00100000 a2.30.7:0 msk off off mask. when the bits are set to 1, corresponding events cause the led to turn off. rw 0000 table 36: common register 9: led2 setting1 (map to tp_phy, reg. 31, page 2 a28 [15:12] = 0010) bit description bit name description mode default a2.31.15:13 reserved reserved r 000 a2.31.12 force led on force led2 on. rw 0 a2.31.11:9 reserved reserved r 000 a2.31.8 force led off force led2 off. rw 0 a2.31.7:0 msk blink blink mask. when the bits are set to 1, corresponding events cause the led to blink rw 10000000 table 37: common register 10: led2 setting2 (map to tp_phy, reg. 29, page 3 a28 [15:12] = 0011) bit description bit name description mode default a3.29.15:8 msk on on mask. when the bits are set to 1, corresponding events cause the led to turn on. rw 00000000 a3.29.7:0 msk off off mask. when the bits are set to 1, corresponding events cause the led to turn off. rw 00000000 table 34: common register 7: led1 setting1 (map to tp_phy, reg. 29, page 2 a28 [15:12] = 0010) bit description bit name description mode default
al2100 preliminary data sheet 11/11/02 broadcom corporation page 30 common registers document al2100-ds01-405-r led3 s etting 1 r egister 11 the default operation for led3 is on on fx_link, blink on remote_fault. led3 s etting 2 r egister 12 led4 s etting 1 r egister 13 the default operation for led4 is on when the result of auto negotiation on twisted pair port is full duplex. led4 s etting 2 r egister 14 table 38: common register 11: led3 setting1 (map to tp_phy, reg. 30, page 3 a28 [15:12] = 0011) bit description bit name description mode default a3.30.15:13 reserved r 000 a3.30.12 force led on force led3 on. rw 0 a3.30.11:9 reserved r 000 a3.30.8 force led off force led3 off. rw 0 a3.30.7:0 msk blink blink mask. when the bits are set to 1, corresponding events cause the led to blink rw 00000100 table 39: common register 12: led3 setting2 (map tp_phy, reg. 31, page 3 a28 [15:12] = 0011) bit description bit name description mode default a3.31.15:8 msk on on mask. when the bits are set to 1, corresponding events cause the led to turn on rw 01000000 a3.31.7:0 msk off off mask. when the bits are set to 1, corresponding events cause the led to turn off. rw 00000000 table 40: common register 13: led4 setting1 (map to tp_phy, reg 29, page 4 a28 [15:12] = 0100) bit description bit name description mode default a4.29.15:13 reserved r 000 a4.30.12 force led on force led4 on. rw 0 a4.29.11:9 reserved r 000 a4.29.8 force led off force led4 off. rw 0 a4.29.7:0 msk blink blink mask. when the bits are set to 1, corresponding events cause the led to blink rw 00000000 table 41: common register 14: led4 setting2 (map tp_phy, reg 30, page 4 a28[15:12] = 0100) bit description bit name description mode default a4.30.15:8 msk on on mask. when the bits are set to 1, corresponding events cause the led to turn on. rw 00010000 a4.30.7:0 msk off off mask. when the bits are set to 1, corresponding events cause the led to turn off. rw 00000000
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r common registers page 31 section 5: 4b/5b code-group table table 42: 4b/5b code-group table symbol name 4b code 5b code description 0 0000 11110 data 0 1 0001 01001 data 1 2 0010 10100 data 2 3 0011 10101 data 3 4 0100 01010 data 4 5 0101 01011 data 5 6 0110 01110 data 6 7 0111 01111 data 7 8 1000 10010 data 8 9 1001 10011 data 9 a 1010 10110 data a b 1011 10111 data b c 1100 11010 data c d 1101 11011 data d e 1110 11100 data e f 1111 11101 data f idle and control code i 0000 11111 idle j 0101 11000 start of stream delimiter, part 1 of 2; always use in pair with k symbol. k 0101 10001 start of stream delimiter, part 2 of 2; always use in pair with j symbol. t undefined 01101 end of stream delimiter, part 1 of 2; always use in pair with r symbol. r undefined 00111 end of stream delimiter, part 2 of 2; always use in pair with t symbol. invalid code h undefined 00100 transmit error; used to send halt code-group v undefined 00000 invalid code v undefined 00001 invalid code v undefined 00010 invalid code v undefined 00011 invalid code v undefined 00101 invalid code v undefined 00110 invalid code v undefined 01000 invalid code v undefined 01100 invalid code v undefined 10000 invalid code v undefined 11001 invalid code
al2100 preliminary data sheet 11/11/02 broadcom corporation page 32 common registers document al2100-ds01-405-r section 6: smi read/write sequence table 43: smi read/write sequence preamble (32 bits) start (2 bits) opcode (2 bits) phyad (5 bits) regad (5 bits) turn around (2 bits) data (16 bits) idle read 1?1 01 10 aaaaa rrrrr z0 d?d z write 1?1 01 01 aaaaa rrrrr 10 d?d z
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r absolute maximum ratings page 33 section 7: electrical specifications the following electrical characteristics are design goals rather than characterized numbers. a bsolute m aximum r atings r ecommended o perating c onditions e lectrical c haracteristics table 44: absolute maximum ratings parameter symbol min max units supply voltage vcc gnd-0.3 2.625 v storage temperature ts -40 +125 c electrostatic discharge vesd 1000 v table 45: recommended operating conditions parameter symbol pin operating mode min max units supply voltage vcc vcc 2.375 2.625 v high-level input voltage v ih all digital inputs 2 v low-level input voltage v il all digital inputs 0.8 v pecl low-level input voltage v il sd 100basefx 1.7 v pecl high-level input voltage v ih sd 100basefx 2.2 v differential input voltage v idiff fip/fin 100basefx 1.4 1.8 v common mode input voltage v icm rxp/rxn 100basetx 1.8 vcc v common mode input voltage v icm fip/fin 100basefx 1.8 2.2 v ambient operating temperature t a -40 +85 c table 46: electrical characteristics parameter symbol pins conditions min max units supply current i cc vcc,vccpll vcc= 2.5v +/- 5% 154 ma supply current power down mode i cc vcc,vccpll 100base-tx 100base-fx 20 ma high-level output voltage v oh all digital outputs i oh = -4ma vcc= 2.5v +/- 5% 2v high-level output voltage v oh txp/txn driving load magnetic module vcc+1.5 v low-level output voltage v ol all digital outputs 0.4 v
al2100 preliminary data sheet 11/11/02 broadcom corporation page 34 electrical characteristics document al2100-ds01-405-r low-level output voltage v ol txp/txn driving load magnetic module vcc-1.5 differential output voltage v odiff fop/fon 100base-fx 1.4 1.8 v input current i i digital inputs w/pull- up resistor v i = vcc +200 a input current i i all other digital inputs vcc v i gnd 100 a bias voltage v bias rbiad 1.18 1.30 v table 46: electrical characteristics (cont.) parameter symbol pins conditions min max units
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r clock timing page 35 section 8: timing an d ac characteristics c lock t iming r eset t iming figure 5: reset timing table 47: clock timing parameter symbol min typ max units xtal input cycle time ck_cycle 40 ns xtal input high/low time ck_hi ck_lo 20 ns xtal input rise/fall time ck_edge 4 ns table 48: reset timing parameter symbol min typ max units reset pulse length low period with stable xtal input reset_len 1 s activity after end of reset reset_wait 1 second ck25 re s et # normal phy be gi n he re re se t _ len reset_wait ck_hi ck_cyc le ck _e dg e ck_lo ck_edge activity may reset_ edge reset_edge
al2100 preliminary data sheet 11/11/02 broadcom corporation page 36 reset timing document al2100-ds01-405-r m anagement d ata i nterface t iming figure 6: management interface timing table 49: management interface timing parameter symbol min typ max units mdc cycle time mdc_cycle 40 ns mdc high/low 20 ns mdc rise/fall time mdc_rise mdc_fall 10 ns mdio input setup time to mdc rising mdio_setup 10 ns mdio input hold time from mdc rising mdio_hold 10 ns mdio output delay from mdc rising mdio_delay 0 30 ns mdc mdio (into al2100) mdio (from al2100) mdc_cycle mdc_fall mdc_rise mdio_setup mido_hold mdio_setup mido_hold mdio_delay
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r reset timing page 37 section 9: tx application termination figure 7: tx application auto mdi/mdix magnetics: bel: s558-5999-w2; pulse: h1102; halo: tg110-s050n2 txp txn 3 8 5 1:1 1:1 auto mdi/mdix 2 rxn 7 6 al2100 rxp tp application 1 rj45 4 2.5v 2.5v c3 .1uf c1 .1uf r6 75_1/16w_5% r7 75_1/16w_5% c5 1000pf_2kv r2 49.9_1/16w_1% r1 49.9_1/16w_1% c2 .1uf r8 75_1/16w_5% r4 49.9_1/16w_1% r3 49.9_1/16w_1% r5 75_1/16w_5% c4 .1uf
al2100 preliminary data sheet 11/11/02 broadcom corporation page 38 reset timing document al2100-ds01-405-r section 10: fx application termination please contact altima communications, inc. for the latest component value recommendation. figure 8: fx application z=50 ohm z=50 ohm z=50 ohm fx application z=50 ohm z=50 ohm z=50 ohm z=50 ohm z=50 ohm z=50 ohm al2100 fon fin fip fx_dis fop sd/fxen_b 3_3v 2_5v 3_3v 3_3v 3_3v 3_3v c9 .1uf c8 .1uf r8 49.9 r12 130 r4 2k r15 20k l2 blm11a601s c10 .1uf r16 20k r19 82 l1 blm11a601s r14 82 c5 0.01uf r7 5k r13 130 e c b q1 ztx795a e b c c6 .1uf c11 .1uf r10 13k r11 13k c2 .1uf c1 .1uf c12 1uf j1 hfbr-5903 9 3 4 5 10 2 6 1 7 8 td+ sd rd- rd+ td- rxvcc txvcc rxvee txvee nc e c b q2 2n2222a e b c c3 10uf r9 49.9 c4 0.01uf c7 .1uf r5 130 r1 5k r18 20k r17 20k r2 499 r20 82 r3 200 r6 5k
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r reset timing page 39 section 11: power and ground filtering figure 9: power and ground filtering vcc vcc vcc .01uf 2.2uf 2.2uf .1uf .1uf .1uf .01uf .1uf .1uf power connections for al2100 place the capacitor as close as possible to each power pin. al2100 vccpll place these capacitors next to pins 1, 10, 18, 25, 36, and 41.
al2100 preliminary data sheet 11/11/02 broadcom corporation page 40 reset timing document al2100-ds01-405-r section 12: package dimensions (48-pin tqfp) figure 10: quad flat pack outline (7 x 7 mm)
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r reset timing page 41 section 13: thermal characteristics table 50: thermal characteristics airflow (feet/minute) 0 100 200 400 600 theta ja ( c/w) 53.9 c/w 51.2 c/w 50 c/w 48.6 c/w 47.5 c/w table 51: maximum junction temperature theta jc theta jc ( c / w) at max junction temperature of 125 c 24.7 c/w
al2100 preliminary data sheet 11/11/02 broadcom corporation page 42 reset timing document al2100-ds01-405-r section 14: ordering information part number package ambient temperature al2100kqt 48tqfp 0 to 70 c al2100iqt 48tqfp -40 to 85 c
preliminary data sheet al2100 11/11/02 broadcom corporation document al2100-ds01-405-r reset timing page 43
document al2100-ds01-405-r broadcom corporation 16215 alton parkway p.o. box 57013 irvine, ca 92619-7013 phone: 949-450-8700 fax: 949-450-8710 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, f unction, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. al2100 preliminary data sheet 11/11/02

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